The present invention relates to non-volatile memory cells and, more particularly, to electrically erasable and programmable memories of the EEPROM or FLASH EEPROM type comprising memory cells with floating-gate transistors.
In electrically erasable and programmable memories, the value of a bit stored in a memory cell is represented by a remanent electrical characteristic of the cell which may be modified by cell-erasing or cell-programming operations to record a logic 1 or a logic 0.
More particularly, the programming or erasure of a memory cell comprising a floating-gate transistor includes the injection or extraction of electrical charges in the gate of the transistor by a tunnel effect (Fowler-Nordheim) or by hot electron injection using a high programming or erasure voltage VPP in the range of 10 to 20 V. The electrical charges injected or extracted from the floating gate determine the threshold voltage Vt of the transistor which thus forms the remanent electrical characteristic representing the bit stored in the memory cell.
The reading of a memory cell comprising a floating-gate transistor thus includes comparing the threshold voltage Vt of the transistor with a reference voltage Vt0. Which is substantially midway between the negative threshold voltage of a programmed transistor and the positive threshold voltage of an erased transistor. It is assumed that the threshold voltage Vt of the transistor will remain stable in time, which is normally for several years under specified conditions of temperature and use. In other words, the electrical charges injected into the gate of the transistor remain indefinitely trapped therein so long as a reverse erasure operation is not performed, and the extracted electrical charges do not return into the erased gate so long as a reverse programming operation is not performed.
However, it may happen that manufacturing defects affect the stability of certain cells, occasionally leading to an error in the reading of a bit. For example, the negative threshold voltage of a programmed transistor, which conventionally represents a bit at a logic 1, may develop slowly towards a positive value. So long as the threshold voltage remains below the reference voltage Vt0, the transistor is considered to be programmed. However, the threshold voltage can also develop substantially beyond the reference voltage Vt0. There is then a data corruption so that a logic 0 is read in the memory instead of the initially recorded logic 1, or vice versa.
For this reason, a non-volatile memory is generally provided with an error correction circuit to detect and correct an erroneous bit in a string of bits using an error correction code (ECC). The error correction code is inserted into the string of bits when it is being recorded in the memory, and is computed by a specific algorithm, such as the Hamming algorithm, for example, which is well known to those skilled in the art.
The drawback of the Hamming algorithm and, more generally, of any prior art error correction algorithm is that it generates codes of a length that are not negligible with respect to the number of bits to be secured. Planning for a correction mode of this kind complicates the architecture of the memory because of the number of additional memory cells that have to be planned for its recording. Furthermore, the longer the correction code, the more complex is the error correction circuit.
FIG. 1 provides a schematic view of the architecture of a memory MEM1 comprising word lines WL0 to WLN and bit lines BL0 to BL11. The memory MEM1 is provided with a word line decoder WLD, a bit line decoder BLD and a read circuit SA with twelve elementary circuits SA0 to SA11, which are known as sense amplifiers. Each word line WLl has eight data bits b0 to b7 and four check bits b8 to b11 forming, for example, a Hamming code used to detect and correct an erroneous bit among the twelve bits b0 to b11.
When a word line is selected by the decoder WLD and the corresponding cells are activated in a read mode by the decoder BLD, the read circuit SA delivers the twelve bits b0 to b11 of the selected word line. The bits b0 to b11 are sent to a correction circuit DCC which delivers the eight data bits b0 to b7 at an output after having detected and corrected an erroneous bit as the case may be.
The drawback of a memory of this kind is that it comprises 33% of cells reserved for the detection and correction of the possible malfunctioning in the other memory cells.
One approach to reduce the size of the error correction codes in non-volatile memories is disclosed in European patent application EP 307,958, which discloses an EEPROM memory comprising sense amplifiers delivering data bits, and error signals when the threshold voltage of a memory cell is in a forbidden region. As shown in FIG. 9 of this referenced application, the memory comprises an error correction circuit arranged to correct an erroneous bit by inverting the value of the erroneous bit when the corresponding error signal indicates a reading error.
The inversion of the value of the erroneous bit is done by an XOR gate which receives the erroneous bit on its first input and the output of an AND gate on its second input. The AND gate receives on its inputs the signal error and a parity bit computed by a circuit from a string of bits comprising the erroneous bit and a parity bit recorded in the memory. When the parity bit computed by the circuit is at a logic 1, this means that there is an error since the parity bit of a string of bits comprising a parity bit is always at a logic 0.
The XOR gate thus functions as an inverting gate with respect to the erroneous bit received on its other input, and delivers a logic 0 if the erroneous bit is at a logic 1 and a logic 1 if the erroneous bit is at a logic 0. However, this correction method is complex to implement since the implementation of all the XOR gates requires the use of numerous elementary logic gates.
In view of the foregoing background, an object of the present invention is to reduce the size of the error correction codes in non-volatile memories, and simplify the architecture of the memories and the structure of the error correction circuits.
Another object of the present invention is to provide a method of error correction which is relatively straightforward to implement, and which can be implemented using switching circuits, such as multiplexers, with a reduced number of logic gates.
These and other objects, advantages and features are provided by a method for the correction of an erroneous bit in a string of bits, with the method comprising a step of providing, in the string of bits, for a first parity bit computed from the other bits of the string of bits at a point in time when the erroneous bit was valid. The method further comprises a step of computing a second parity bit as a function of all the bits of the string of bits other than the erroneous bit, and a step of replacing the erroneous bit by the second parity bit.
According to one embodiment of the present invention, the erroneous bit receives, by convention, a logic value that has no effect on the parity computation, and the second parity bit is computed from all the bits of the string of bits, including the erroneous bit. The erroneous bit is preferably replaced by the second parity bit using a multiplexer circuit.
According to one embodiment, the string of bits is read in a non-volatile memory.
According to yet another embodiment, to correct more than one bit in a binary word, the string of bits is split up into at least two strings of bits, each comprising a parity bit.
The present invention also relates to a non-volatile memory comprising remanent memory cells, means for reading a string of bits in the memory, and means for the correction of an erroneous bit present in a string of bits read in the memory. The correction means computes a parity bit from the bits of the string of bits and replaces an erroneous bit by the computed parity bit.
According to one embodiment, the reading means are arranged to assign a logic value to an erroneous bit without affecting a parity computation, and the means to compute a parity bit are arranged to receive, at an input, all the bits of the string of bits, including an erroneous bit. The means to replace an erroneous bit by the computed parity bit preferably comprises a multiplexer circuit.
According to one embodiment, the reading means are arranged to deliver a bit having a first logic value when the remanent characteristic of a memory cell is above a first threshold, deliver a bit having a second logic value when the remanent characteristic of a memory cell is below a second threshold lower than the first threshold, and deliver an erroneous bit signal when the remanent characteristic of a memory cell is between the first and second thresholds. The first and second thresholds define a region comprising the domain of the virgin cells or included in the domain of the virgin cells so that the erroneous state of a bit remains stable in time.
The reading means are preferably arranged to deliver a bit having the second logic value when the remanent characteristic of a memory cell is below the first threshold. According to another embodiment, the memory comprises means to compare the current flowing through a cell with two reference currents, and sends the erroneous bit signal when the current flowing through the floating-gate transistor is between the two reference currents.
According to one embodiment, the reading means comprises a first comparator to compare the current flowing through a cell with a first reference current delivering a first bit used as a data bit read in the cell, a second comparator to compare the current flowing through a cell with a second reference current delivering a second bit, and an XOR function to combine the first bit and the second bit and deliver an erroneous bit signal.